Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution

Properties


name
Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution
definition
A processor event may allow transient operations to access architecturally restricted data (for example, in another address space) in a shared microarchitectural structure (for example, a CPU cache), potentially exposing the data over a covert channel.

Neighbors

CWE-1421 has no direct neighbors in this release.

Inferred Relationships

This page is experimental and may change significantly in future releases.

Related Countermeasure Techniques

No related defensive techniques in this release.

Related Weaknesses

Related Offensive Techniques

No related offensive techniques in this release.